Valtrix Systems, an industry leading provider of RISC-V design verification products for building functionally correct CPU and system-on-chip implementations, announced today that UltraRISC, a leading provider of high-performance RISC-V IPs and multi-core processors headquartered in Shanghai, has licensed STING for the design verification of its RISC-V SoC implementations.
STING, a software-driven test stimulus generator from Valtrix, is capable of creating self-checking and architecturally correct portable programs that can be enabled on simulations, emulation, FPGA and silicon.
UltraRISC’s Executive President and CTO, Dr. Jiang Jiang said, “Our company conducts rigorous verification to ensure that our processors are well designed and thoroughly verified. Valtrix’s STING tool has made a significant contribution to our verification efforts on the UltraRISC’s UR-A1 processor core, particularly the hypervisor extension for hardware virtualization. The capability of running tests across simulation and emulations makes it an ideal choice for our DV strategy.”
“We are very excited to collaborate with UltraRISC as a lead partner for enabling STING for SoC verification of their advanced RISC-V implementations on hardware emulation platforms,” said Shubhodeep Roy Choudhury, CEO of Valtrix. “Complementing the cycles run on simulation with testing on emulation, FPGA and post-silicon is critical in ensuring that the CPU and SoC designs are compliant and free of functional errors. STING’s portable stimulus generation capability allows users to run the tests in any device-under-test environment, thus increasing verification reuse and efficiency,” he added.
For more information on Valtrix’s design verification technology and products, visit: https://www.valtrix.in
About Valtrix’s STING Design Verification Tool
STING, the flagship product of Valtrix, is a commercially supported design verification tool for RISC-V based implementations. It can be configured to generate portable bare-metal programs containing self-checking architecturally-correct test stimulus, which can then be enabled on simulation, FPGA prototypes, emulation or silicon.
Headquartered in Shanghai, China, UltraRISC develops high-performance, power-efficient, and intelligent RISC-V IPs and multi-core processors and is dedicated to elevating the global RISC-V ecosystem. The company has three lines (UR-A, UR-AE and UR-E) of IP offerings in its processor core family, and one line of multi-core processors based on UR-A core in its SoC family. These offerings are designed to cover the major computing scenarios, including but not limited to edge computing, desktop, server, cloud, and self-driving use cases.